Current SRAM arrays have a minimum write voltage (Vmin) that is determined by each of the SRAM cells in the array. A lower Vmin provides a lower power usage and better efficiency during write operations. However, as Vmin is reduced, write-ability of the SRAM cell decreases as the threshold voltage (Vt) of the transistors in the SRAM cells cannot be reduced proportionally to the reduction in Vmin. Lower write voltages reduce headroom (e.g., the voltage difference or buffer between an input voltage (VDD) and a threshold voltage (Vt). Current systems utilize write assist techniques to improve the write-ability of a bit-cell.
Current write assist techniques include using a negative bit-line voltage or decreasing the strength of a PMOS (p-channel metal-oxide silicon device) in a latch portion of a bit-cell. However, the negative BL encounters a high resistance on the BL and rapidly dissipates, such that the voltage at a bitcell on a top row is ineffective for adjusting the strength of the passgate. Similarly, decreasing the strength of the PMOS in a latch increases memory errors and reduces reliability of the SRAM cell.